Browsing College of Engineering & Architecture by Subject "Jitter"

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Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops

Tertinek, Stefan ; Feely, Orla (IEEE, 2009-05-24)

Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a ...
Investigation of first-order digital bang-bang phase-locked loops with reference clock jitter

Tertinek, Stefan ; Feely, Orla (IEEE, 2008-10-16)

Bang-bang phase-locked loops (BBPLLs) are a class of PLLs with a binary-quantized phase detector (BPD). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for ...